1. Field of the Invention
The present invention relates to frame detection and generation and, more particularly, to processing multiple independently-clocked data streams.
2. Description of the Related Art
Digital data transmission systems include facilities for frame detection and frame generation. In general, there are two approaches in the prior art for processing the individual data streams.
In a first conventional method, the frame detection and frame generation facilities are placed in directly in each data path in order to preserve the timing of the individual data streams. However, this requires replication of facilities and requires multiple, independent clock domains.
Another conventional approach uses state machine logic to handle multiple data streams by preserving the state of individual data streams in static RAM (random access memory). As used herein “state” or “context” of data streams refers to system register settings of a particular data stream. Each stream is typically processed as follows: (a) the prior state of the state machine is loaded out of RAM; (b) the stream is processed; (c) the current state is saved again; (d) the result is output from the state machine. While this approach is relatively efficient in terms of chip size, it does not preserve the timing of individual data streams.
There is therefore a need for an improved framer array architecture that preserves the timing of individual data streams and requires relatively less chip space.